🔮E10: Pushing Moore's Law to the Limit with High-NA EUV (aka Nanoscale Chip Printing)

Underrated: High-NA EUV will manufacture chips worth $200 billion annually

Jul 27, 2023

Jane Avril by Henri de Toulouse-Lautrec. To create this print, Lautrec used several lithographic stones, one for each color—inky black, acidic orange, yellow, and green.

Stay with me folks, I promise you will want to know more about High-NA EUV lithography. It sounds boring I agree, but, it’s basically going to single-handedly save Moore’s Law. For fun and profit, I’m going to call it ‘chip printing’ which is easier to understand. And High-NA EUV is like ‘nanoscale chip printing’.

See it's easy as cake, simple as whistling Dixi. Here’s how it goes:

An EUV light source generates a beam of 13.5nm wavelength light;
The light reflects off a series of specialized multilayer mirrors;
It goes through a reflective EUV mask containing the chip pattern to be imaged;
The mask reflects the patterned beam onto the wafer substrate coated with EUV photoresist;
A high numerical aperture (NA) of 0.55+ is achieved using precisely figured concave mirrors to focus the light;
… cutting edge chip…. profit.

But that’s all words. You are all here for “ “nanoscale chip printing” aren’t you.

Onwards to the knowledge,

Kind Regards, Lawrence

(P.S. Hollibobs for next two weeks. So you can learn stuff by yourself. Byeee)

TLDR:

Summary: Lithography patterns microchip features by selectively exposing photoresist using masks. As features shrink, advanced techniques like EUV (extreme ultraviolet) provide the resolution needed. High-NA EUV, the next evolution of EUV lithography, utilizes higher numerical aperture optics to continue scaling chip features below 10nm. It enables more precise, densely packed patterns to replace DUV lithography.
Viability (4): The first High-NA EUV systems are being tested now by ASML and chipmakers, with commercial tools expected around 2025-2026. Though considerable engineering hurdles exist in masks, resists, and precision controls, prior EUV learning and supplier competition provide confidence these issues are resolvable on the timeline needed.
Drivers (5): On the supply side, advances in EUV power, collector optics, controls, and modeling have enabled high NA EUV to become viable. For demand, chipmakers are motivated by High-NA EUV's ability to continue feature size scaling, improve pattern fidelity and flexibility, and extend Moore's Law density scaling for performance and cost gains.
Novelty (4): High-NA EUV provides major improvements in resolution, overlay accuracy, defect control, and scalability compared to optical lithography and first-generation EUV. However, it currently lags in maturity, throughput, and 2x cost over Low-NA EUV. Alternatives like electron beam, nanoimprint, and helium metastable could one day offer compelling balance between resolution, accuracy, cost and scale but are all still in early R&D phase.
Diffusion (4): The extremely high scanner costs, infrastructure upgrades needed across the fab and supply chain, and shortage of skilled labor for process integration are key barriers to High-NA EUV adoption. Careful coordination across the semiconductor ecosystem is critical to overcome these challenges and realize the benefits.
Impact (4): With high costs limiting it to sub-10nm chips, High-NA EUV will likely produce around $200 billion annually in advanced logic, analog, photonic and quantum semiconductors. Though constrained in market scope, High-NA EUV enables incremental but meaningful progress in precision patterning, with more disruptive technologies targeting 2030+ timelines.
Timing (Soon: 2025-2030): With the first system live for testing and optimization, High-NA EUV is slated for pilot production in 2023-2024 and volume manufacturing in 2025-2026. Despite engineering hurdles, strong economic incentives and competition make it likely timelines are met for widespread High-NA EUV availability by 2026.
Underrated: Underrated. High-NA EUV is essential for continuing Moore's Law scaling at sub-10nm nodes. Without it, economics of density gains could collapse. The engineering hurdles facing High-NA EUV are substantial but known. Similar challenges arose with standard EUV initially. Through dedication, the industry has overcome complex problems before, giving confidence that High-NA issues are resolvable.
2030 Prediction: High-NA EUV will manufacture chips worth $200 billion annually.

Some of you may choose to bounce now. And good for you. You got your insights. Move on. But come on, before you do. 1 share. That’s all I ask. Just click the link.

Summary

As always over at State of the Future, let’s start from the very top:

Lithography is the process of patterning the tiny features on semiconductor chips. It transfers the circuit patterns onto the silicon wafer surface for forming the transistors and interconnects. Photo-lithography, the only commercial approach to lithography, relies on selectively exposing a light or particle sensitive material (photoresist) using a mask that blocks and transmits the exposure. The exposed photoresist is then developed, leaving a 3D pattern that serves as a template for etching and building up the chip structures through subsequent processing steps. The key is being able to accurately and repeatedly project very small patterns onto the wafer. As chip features shrink, advanced lithography techniques like EUV (Extreme Ultraviolet) are required to provide the resolution needed. Lithography is a crucial step that shapes the design and performance of integrated circuits. You’ve probably come across EUV in the context of ASML, one of the most important companies in semiconductor manufacturing, and probably Europe, because it’s the only company in the World that can make the most advanced EUV machines that make all the World’s cutting edge chips.

Right, with that in hand, High-NA EUV (high numerical aperture extreme ultraviolet lithography) is an advanced method for manufacturing semiconductors. The technology is the next evolution of EUV lithography that will allow continued scaling of chip features by using higher numerical aperture optics. It uses a high numerical aperture (0.55 or higher) and extreme ultraviolet light (13.5 nanometre wavelength) to create incredibly small, intricate patterns on semiconductor wafers for microchips. 0.55+ NA improves the theoretical resolution limit by 30% from current EUV systems.

High-NA EUV is poised to replace existing deep ultraviolet (DUV) lithography and first-generation EUV lithography, as it allows for more precise and densely packed features on a chip. EUV lithography was introduced in the last few years to enable patterning of smaller features down to around 30nm. With High-NA EUV chipmakers are aiming to pattern features down to 10nm and below.

Sidebar: You may have heard of 3nm and 5nm process nodes from TSMC and Intel. The "node names" can be confusing in relation to the actual physical gate lengths and pitches being patterned. The process nodes like 3nm, 5nm etc. are marketing names that denote generations of chip manufacturing process technology. They do not directly correspond to any physical feature size. The physical feature sizes are things like gate length (the length of a transistor gate) and metal pitch (spacing between wires). These are measured in nanometers. TSMC's 5nm node has a gate length of 25nm and metal pitch of 42nm. Their 3nm node likely has a gate length around 18nm.

TLDR: Lithography patterns microchip features by selectively exposing photoresist using masks. As features shrink, advanced techniques like EUV provide the resolution needed. High-NA EUV, the next evolution of EUV lithography, utilizes higher numerical aperture optics to continue scaling chip features below 10nm. It enables more precise, densely packed patterns to replace DUV lithography.

Viability (4)

The first High-NA system, completed in 2023, is being used by Imec and ASML customers for research and development purposes. As for commercial availability, High-NA EUV systems are expected to hit the market around 2025-2026. Here's a rough timeline:

2022-2023: ASML ships the first 0.55 NA High-NA system to imec. Used for extensive testing and optimization.
2023-2024: High-NA enters pilot production at select chipmakers to validate process integration. Still very limited availability.
2025: High-volume manufacturing (HVM) tools with High-NA EUV start shipping to chipmakers like TSMC, Samsung, Intel. This is when it will be widely adopted in production fabs.
2026: High-NA becomes more widely available. Multiple fabs equip High-NA tools for critical layers needing the highest resolution.

While the fundamentals are in place, there are considerable engineering hurdles to overcome in masks, resists, controls and system design to fully leverage the higher NA optics.

Mask: the mask must be defect-free over a much wider field to support 0.55+ NA. New defect inspection and repair methods are needed. Absorber thickness and optimization must be adjusted to account for shadowing effects at higher NA. And out-of-band radiation can cause unwanted reflections and image distortion. New filtering techniques may be needed.
Resists: higher sensitivity resists with low line edge/width roughness are required for smaller feature patterning. And resists must maintain performance at higher dose requirements of High-NA systems.
Precision Controls: vibration, thermal stability and wafer stage accuracy requirements become much tighter at higher NA. And better correction of lens heating and thermal aberrations will be critical.

I assume these are difficult but not insoumoutable engineering challenges that will be solved in a timely fashion. First, the entire industry is heavily invested in making the technology work and early systems are already being tested. Second, when EUV was first introduced, there were also many issues predicted with resists, source power, defects etc. But it improved much faster than expected. High-NA can leverage this experience. Lastly, unlike 1st generation EUV, there is some supplier competition, with ASML facing real competition from Nikon and Canon. This incentive will drive rapid progress.

TLDR: The first High-NA EUV systems are being tested now by ASML and chipmakers, with commercial tools expected around 2025-2026. Though considerable engineering hurdles exist in masks, resists, and precision controls, prior EUV learning and supplier competition provide confidence these issues are resolvable on the timeline needed.

Drivers (5)

Supply: Incremental advances across the lithography supply chain over the past 5+ years in areas like EUV power, defect reduction, precision control, and modeling have enabled the complex technology like high NA EUV to become manufacturable. The biggest innovations have been in EUV source power scaling and collector mirror improvements. The EUV light source has scaled up significantly in power over the past decade, from less than 10 watts to over 350 watts. This enables the higher throughput needed for high NA. The collector mirrors play a critical role in gathering the EUV light generated by the source and directing it onto the wafer. Past collectors used bare silicon mirrors. But silicon deforms over time from EUV exposure. New materials like silicon carbide (SiC) have much higher stability allowing for higher collection efficiency. Reflectivity has improved from around 65% to now over 80% for SiC multilayers.

Demand: Moore’s Law, etc, etc. But there are a few specific drivers that are motivating chipmakers to adopt High-NA EUV lithography. First, feature size scaling. The higher resolution of High-NA EUV allows continued shrinkage of features like gate length and metal pitch. This extends Moore's Law density scaling for higher performance and lower cost per transistor. Second, pattern fidelity. The tighter pitching enabled by High-NA EUV reduces dimensional variations, allowing more complex designs and patterns. This improves yield and power efficiency. Finally, design flexibility. The resolution boost from High-NA provides more options for chip designers in terms of floorplans, standard cells, and layout. This allows performance optimization.

TLDR: On the supply side, advances in EUV power, collector optics, controls, and modeling have enabled high NA EUV to become viable. For demand, chipmakers are motivated by High-NA EUV's ability to continue feature size scaling, improve pattern fidelity and flexibility, and extend Moore's Law density scaling for performance and cost gains.

Novelty (4)

High-NA EUV competes with other photo-lithography techniques for semiconductor manufacturing.

Optical lithography - wavelengths from 436nm (g-line) to 365nm (i-line)
Deep ultraviolet (DUV) - wavelength from 248nm to modern 193nm
Extreme ultraviolet (EUV) - 13.5nm wavelength
- Low NA EUV (0.33 NA)
- High NA EUV (0.55+ NA)
Electron beam lithography
Directed self assembly (DSA)
Nanoimprint lithography
Maskless lithography (ML2)
Interference lithography
Two-photon lithography
Helium metastable lithography

The axis of competition are:

Resolution - The smallest feature size that can be printed.
Overlay accuracy - Precise alignment between layers nanometer-scale.
Throughput - Number of wafers processed per hour. Drives production volume.
Defect control - Ability to avoid yield limiting defects.
Cost - Initial system cost and cost per wafer.
Complexity - Process complexity impacts ease of use and integration.
Scalability - Ability to extend to future smaller features.
Maturity - Production-readiness and reliability.

TLDR: High-NA EUV provides major improvements in resolution, overlay accuracy, defect control, and scalability compared to optical lithography and first-generation EUV. However, it currently lags in maturity, throughput, and 2x cost over Low-NA EUV. Alternatives like electron beam, nanoimprint, and helium metastable could one day offer compelling balance between resolution, accuracy, cost and scale but are all still in early R&D phase.

Diffusion (4)

Assuming technical maturity, the three main barriers to adoption: cost, infrastructure readiness, and supply chain readiness. Current estimates put the cost of a high-NA EUV scanner around $300+ million, compared to about $150 million for present-day EUV systems with 0.33 NA. The costs are driven by the fact the higher NA optics require more sophisticated mirror and lens components that are challenging to manufacture. This accounts for a significant portion of the increased cost. Additional cost comes from the need for added mechatronics to deal with the extreme precision requirements for vibration, thermal stability, stages, etc. And from the higher NA causes throughput of wafers per hour to drop, meaning more tools are needed in a fab. High-NA EUV will also require significant infrastructure upgrades and process changes. This includes new defect-free mask handling, track systems, resists, and potentially major fab modifications. Fabs need time to implement all these changes for a smooth rollout. This is true for the broader supply chain, with upstream suppliers like mask blanks, resists, photoresists, optics and other key components need to be ready in volume. Any delays in these supply chains could impede High-NA adoption. There are concerns about having enough skilled labor as well. (See TSMC says skilled worker shortage delays start of Arizona chip production)

Careful orchestration across the ecosystem is required to reap the benefits. But the motivation is there, given the value High-NA brings to scaling and enabling future chip generations like 2nm or 1.4nm nodes.

TLDR: The extremely high scanner costs, infrastructure upgrades needed across the fab and supply chain, and shortage of skilled labor for process integration are key barriers to High-NA EUV adoption. Careful coordination across the semiconductor ecosystem is critical to overcome these challenges and realize the benefits.

Impact (4)

Unless total failure, for which I assign a low probability, the only plausible scenario for High-NA EUV is that is serves the sub-10nm chip patterning market. The 2x cost over low-NA EUV and the 5x higher cost that DUV makes it unlikely to win market share in the 10-45nm range. <10nm was ~3% of total wafer volume in 2021 growing to 10-15% by 2025. So we are looking at roughly 15% or less of total semiconductor output, albeit, the high value output and the chips that will push forward state-of-the-art in, AI, robotics, wearables, etc. Note, NA-EUV is not limited to manufacturing digital chips and can be used to produce semiconductor devices including quantum, analog, and photonic. Although, photonic ICs also require deposition of specialized materials like silicon nitride, silicon oxynitride, or indium phosphide. EUV cannot deposit these materials, so it’s is done by techniques like CVD or epitaxial growth. Based on these rough assumptions, it’s plausible that high-NA EUV will manufacture chips worth $200 billion annually.

High-NA EUV will bring meaningful progress on chip scaling, performance, power efficiency, and capabilities across a range of semiconductor applications over the next decade. These benefits will be compounded by the progress of analog, photonic and quantum chip which will very likely be manufactured using the technology. High-NA EUV is the epitome of an incremental technology. In terms of long-term impact, we have a few disruptive technologies like E-Beam, nanoimprint, and helium metastable, but as of today the resolution, scalability, and cost trade-offs are unknown.

TLDR: With high costs limiting it to sub-10nm chips, High-NA EUV will likely produce around $200 billion annually in advanced logic, analog, photonic and quantum semiconductors. Though constrained in market scope, High-NA EUV enables incremental but meaningful progress in precision patterning, with more disruptive technologies targeting 2030+ timelines.

Timing (Soon: 2025-2030)

One system live in use by imec and ASML for testing and optimization. Planned pilot production in 2023/2024 at select chipmakers to validate process integration. With high-volume manufacturing scheduled to begin in 2025 with tools shipping to TSMC, Samsung, Intel. With 2026 at the most likely year for widespread availability. As noted, hitting these timelines require overcoming some sizable engineering challenges and so are at risk of slipping. But also as mentioned, the orchestration needed in the supply chain to achieve large volumes will mean there is a huge economic incentive to hit deadlines. The presence of Nikon and Canon in the market also makes it more likely that ASML won’t miss deadlines and demand will be met. We should expect with high probability that High-NA EUV hits in the market from 2026.

TLDR: With the first system live for testing and optimization, High-NA EUV is slated for pilot production in 2023-2024 and volume manufacturing in 2025-2026. Despite engineering hurdles, strong economic incentives and competition make it likely timelines are met for widespread High-NA EUV availability by 2026.

Overrated or Underrated?

Underated. High-NA EUV is essential for continuing Moore's Law scaling at sub-10nm nodes. Without it, economics of density gains could collapse. The engineering hurdles facing High-NA EUV are substantial but known. Similar challenges arose with standard EUV initially. Through dedication, the industry has overcome complex problems before, giving confidence that High-NA issues are resolvable.

2030 Prediction

High-NA EUV will manufacture chips worth $200 billion annually

Assumptions

In 2021, less than 3% of total semiconductor volume was produced at <10nm node.
By 2025, <10nm is forecast to reach 10-15% market share
By 2030, I’ll use IDC’s most ambitious forecast of $1.14 trillion for entire semiconductor market
Assuming <10nm could account for 20-30% of total semiconductor production by the end of the decade driven by AI, HPC and wearables/edge.
$1.14 trillion x 0.25 = $285 billion TAM

Open Questions

Geopolitics

What will the export regime on NA-EUV look like? We have to assume ASML first, and Nikon and Canon, too, will be unable to sell into China and potentially other markets like Russia too. How will this impact investments and the economics?
Governments may invest in new players for High-NA EUV outside the concentrated triopoly to spur competition. Thus certainly is happening in China.
Based on this, alternative lithography routes, even at technical compromise, may get prioritized for greater supply diversification. This may give a headwind for emerging techniques like e-beam, nanoimprint and helium metastable in particular.

Technical

Mask defects - Can mask defectivity be reduced to viable levels for high volume manufacturing? Tighter specifications are needed on multilayer deposition quality and substrate defects.
Line edge/width roughness - Can excellent line edge roughness and critical dimension uniformity be maintained with High-NA EUV at full production? This impacts yield and tolerances.
System productivity - What level of throughput (wafers per hour) can High-NA EUV deliver? And will EUV power sources scale to support improved productivity?

Startups to Watch

EUV/High-NA supply chain:

RESCAN - Developing ultra-smooth mirrors/optics for EUV using ion beam figuring. Potential to supply collector optics.
Komoku - Working on next-gen EUV mask inspection tools, could help address mask defect challenges.
Inpria - Focused on higher-sensitivity EUV resists to improve productivity. Acquired by Merck.
Eigen X - Novel EUV and DUV photoresists using molecular templating. Aims to enhance line edge roughness.
Multibeam - Laser-based maskless lithography concept to complement EUV. Could help with masks.
Veeco - Provides EUV collector protection layers; also has broader process equipment.
NuFlare - Alternative EUV light source supplier to put pressure on ASML.

Nanoimprint Lithography:

Obducat - Provides nanoimprint lithography equipment and resists. Focused on nanopatterning applications.
NIL Technology - Developing roll-to-roll nanoimprint solutions for high-throughput production.

Helium Metastable Lithography:

Lace Lithography - Alternative Metastable Helium approach

E-Beam:

JEOL - Major supplier of electron beam lithography equipment for mask production. Working on high-throughput e-beam tools.
IMS Nanofabrication - Developing novel multi-beam electron optics for direct e-beam wafer patterning.

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