The Future of Computing is Glass w/ Andrea Rocchetto of Ephos

will photonic chips be put in glass?

I’m Lawrence, a pleasure. I invest in people making the world better for my children. pre-seed/seed. About to launch Europe’s first dedicated semiconductor fund. More soon. msg: lawrence@cloudberry.vc. x x

Andrea Rocchetto is the founder of Ephos, a company developing glass-based photonic substrates for next-generation semiconductor packaging. Our conversation explored why the semiconductor industry is shifting from shrinking transistors to connecting chiplets, and why glass may become the foundation for this new computing architecture. This matters because the companies that master advanced packaging and photonic interconnects will likely dominate the next decade of computing infrastructure.

Why This Is Important

The packaging revolution is underestimating how big things need to get. While most attention focuses on making transistors smaller, the real action is happening at the system level. Companies like Intel are already working on glass substrates measuring one meter by one meter, a dramatic shift from the miniaturisation narrative that dominates semiconductor coverage. This is the Cerebras bet validated at the substrate level.

Glass solves three problems simultaneously that silicon cannot. Organic substrates warp when heated, limiting trace alignment precision. Silicon interposers are expensive and size-constrained. Glass offers dimensional stability, panel-scale manufacturing, and the ability to embed photonic waveguides directly into the packaging substrate, eliminating an entire layer of complexity from chiplet architectures.

Quantum and classical computing are converging on the same requirements. Both data centres and quantum photonic systems need ultra-low-loss optical components with fast switching. This means companies building for one market are inadvertently building for both, creating unexpected synergies between seemingly distant applications.

Interview

Let’s start with chiplets. What are they and why do they matter?

For the last several decades, the way we made better computers was by making transistors smaller and smaller. That is known as Moore’s Law. We have very much reached the point where we cannot make them much smaller. There might be some margins still, but they are now very thin. Definitely not doubling every two years, which was the original statement of Moore’s Law.

The consensus in the industry is that the way we are going to get better computation is by going more at the system level. The big advances are going to happen through better architectures, better chip layouts, better connectivity.

So when people talk about 5nm or 3nm nodes, where does that fit in this picture?

The way I very much see computation is under the lens of FLOPS [Floating Point Operations Per Second] per joule, so how much computation you can get per unit of energy. I think this is a better metric than transistor dimension or transistor density. That has followed an exponential curve. If we want to keep getting there, we must find solutions that go beyond just making transistors smaller.

One of these tools is breaking up existing chips into smaller pieces. These smaller pieces are called chiplets. Not every part of a chip needs to be cutting edge. The more cutting edge you are, the harder it is to manufacture that component, the more expensive it is. Bringing everything together in a single chip might not be the optimal solution.

What the industry is going after is breaking computation into smaller chips that are more specialised. We might use a more complex and expensive manufacturing node for very specialised AI accelerators, and use older manufacturing nodes that are cheaper and more reliable for parts that are less demanding from a computational standpoint.

Help me visualise this. Should I imagine a CPU connected to a network switch connected to memory, all on the same die?

The level of disaggregation can be pushed almost as much as you want. Think of a Lego spacecraft model all casted in a single piece, or made by smaller Lego pieces that ultimately produce the same spacecraft. The level of detail you want to reach is very much dependent on specific needs and cost considerations.

This chiplets approach is very much shifting the problem to a packaging problem. We need to essentially glue and connect all these different chiplets together on a single substrate. This substrate needs to be big enough to have enough real estate to host all those different chiplets and provide good enough connectivity among them.

Why not just use silicon? We have a lot of it and it is cheap.

If we wanted to just have one gigantic chip on a single wafer, which is an approach companies like Cerebras are following, you pay two different prices. One is reliability. Many parts of your wafer are just not going to be manufactured correctly, they have malfunctions or errors. The solution is to add redundancy, but then you cannot use the entire wafer space for computation.

That approach might work for some very specialised AI applications where you can afford to pay an extremely high price for wafers that are error free. But for many other applications, you will want to break up into little pieces and bond them on a substrate.

So everyone is moving to chiplets. Where does Ephos fit in?

The standard at the moment is organic substrates. There are films built by Ajinomoto, the same company that invented the process to synthesise MSG, the food enhancer.

Wait, the MSG company makes semiconductor substrates?

They were producing a ton of MSG and trying to figure out what they could do with the byproducts of their manufacturing process. This organic film that is now widely used in the semiconductor industry comes from Ajinomoto, this Japanese company.

But organic substrates have a challenge: dimensional stability. As they heat up and cool down during manufacturing, they warp. For building all the traces that connect the different chiplets, you use a process where you build traces layer by layer, heating and cooling your substrate each time. If your substrate warps and changes dimension, it is very hard to align these traces.

One option is silicon interposers rather than organic substrates. But the challenge is twofold. Cost, and the substrates we can manufacture tend to be relatively small. You cannot have very large silicon substrates. With chiplet architectures, we really want to go to panel-scale integration.

That sounds more like a solar panel than a chip

For advanced computation, yes. Intel, which has pioneered work on glass substrates, was working on panels with 515mm x 510mm. This is not well understood outside our industry.

Glass solves both problems. It offers dimensional stability, and glass is a very cheap material that you can easily scale to panel scale.

So chiplets are the trend. But there is another trend here around photonics. How does that fit?

As soon as you start to glue all these chips together on a substrate, you have the problem of how to connect them and move information from one place to another. Traditionally this always happened with copper and electronics. But that is also hitting a barrier in terms of performance.

Photonics very much stopped at the large scale in terms of adoption. Our conversation today is enabled by optical fibres, which are glass made. For long distance communications, photonics is the standard. But the smaller the scale, the less photonics has made sense. Things are changing.

What is changing the equation?

Two factors: energy cost and bandwidth. If you look at FLOP density, it increased 60,000 times over the last 20 years. But interconnect bandwidth increased only by 30 times. We have so much more computing power, but so much less ability to move information around at the chip level.

The issues limiting photonics at chip scale have been miniaturisation and reliability. Lasers can be power hungry and very unreliable. The cost of electro-optical conversion essentially erased all the benefits. But you have Nvidia and Broadcom announcing co-packaged optics chiplets. These are tiny chiplets that perform electro-optical conversion, turning electrical signals into optical signals and vice versa.

Lasers are the bottleneck then?

Yes, and that is why companies like Avicena and Microsoft are pursuing a very different approach, one that does not use lasers but micro-LEDs. You can avoid the power and reliability problems of lasers entirely.

But we still have pluggables in data centres. Do they still have a role if we are moving to co-packaged optics?

Absolutely. The reliability question is more about ease of maintenance. You can easily swap a broken pluggable. But if you have your co-packaged optics chiplet packaged onto a substrate and your package costs, say, ten thousand dollars, if the optical component breaks you throw away the entire thing.

Where does glass photonics come in specifically?

What we at Ephos are trying to do is say: why do you not use the glass substrate on which you are packaging your chiplets, independently from photonics, as a photonic network for chip-to-chip connectivity?

We have some of the best performing waveguides [structures that propagate light in a controlled way, like optical fibres but integrated into a chip] in the world in terms of losses. Not the best ever built, those are in optical fibres. But for integrated photonic circuits, we have some of the best.

Why are yours better?

They are solid state, built inside a material rather than on top of a silicon substrate with a lithographic process. From a manufacturability point of view, this gives you certain advantages. You need a much less clean environment because the manufacturing process happens inside the substrate.

For chiplet-to-chiplet connectivity specifically, you can just use the substrate you are already using to package the chiplets. One advantage is better performing waveguides. Another is you do not need an extra layer. If you use silicon photonics for networking, you need to package a silicon photonics chiplet that does just networking. That is one extra layer of complexity, cost, and potential source of errors.

Glass is also great for interfacing with optical fibres. You do not lose any energy at the interface between chip and optical fibre.

This sounds like a first principles pitch. But the risk is you need to build your own fab.

Not only would I have to, I want to. That is how you build a formidable moat. The big chip manufacturing companies of the future are going to be packaging companies. Companies that can integrate lots of different chiplets on a single substrate and are masters of building connections among them. The connections are going to be photonic based and are going to happen on glass. Mastering both design and manufacturing will give the company a very deep moat.

What is the main drawback of glass photonics?

The curvature radius of our waveguides is fairly large. We cannot have very tight bends. Very similar to an optical fibre, you cannot bend it 180 degrees or you will lose all your light. This means certain components, like ring resonators [fundamental building blocks used for modulation and filtering in photonics], we cannot build in tiny form factors.

Even if you want to do computation like optical computing, you need lots of cascaded components. With our technology, the circuits become longer. But you do not really have this issue with large glass substrates, where you are not limited by space. That is why it is a perfect application for glass photonics.

How does quantum computing fit into this picture?

There is a very significant overlap. If you are targeting quantum applications, at some point you will need photonic components because photons are the only truly good carrier of quantum information. It is very hard to move quantum information with electrons or atoms except in very specific settings.

Whenever you hear the word quantum, you must think: you need to be extremely delicate, extremely precise. You never want to lose anything. So quantum photonics wants all components to be as lossless as possible.

And guess what the data centre and chip industry wants? They want low loss too. Losing light means losing energy and losing information. This is very much where the two fields are intersecting.

What else do quantum and classical have in common?

There is a strong emphasis on modularity. You are not going to build gigantic integrated photonic circuits with millions of components. All the top photonic quantum computing companies, Xanadu, PsiQuantum, Quandela, they are all targeting highly modular architectures where the integrated photonic circuits are actually fairly simple.

The key performance parameters are speed of the modulators, losses inside the chip, and critically losses in connecting chip with optical fibres. The chips are going to be connected by optical fibres and you want very low coupling losses.

Let me try to summarise. You are betting on chiplets, which seems like a standard industry bet. You are betting on photonic devices, which is debatable on exact timelines but the growth is real. And your specific bet is that glass is the best substrate to connect these devices, with silicon photonics being ill-suited on some timeline.

I totally subscribe to that. I would only add that I do not think silicon photonics will disappear. There are lots of interesting applications where silicon photonics is great. But for this specific task of building on-chip connectivity with photonics, glass has an edge in cost, pure photonic performance, and packaging.

What has historically limited glass photonics is something which is not a problem for large scale applications. The large curvature radius constraint matters for tiny circuits, not for meter-scale substrates connecting chiplets.

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Debrief

Bear case for what he said:

I mean, I know we say it all the time, but maybe this time really is different? The semiconductor industry genuinely is hitting interconnect bottlenecks. The 60,000x versus 30x figure on compute density versus bandwidth is real and well documented. Chiplets are not a speculative bet, they are already shipping in AMD Ryzen, Intel Ponte Vecchio, and elsewhere. The move to advanced packaging is consensus.

Glass substrates are also not speculative. Intel announced their glass substrate programme publicly. The dimensional stability problem with organic substrates is a known pain point. The physics here is straightforward: glass does not warp, organics do, and trace alignment matters more as features shrink.

On photonics, the energy economics are shifting. Co-packaged optics announcements from Nvidia and Broadcom at OFC 2024 signal that the major players see electrical interconnects running out of runway. The conversion cost that used to kill photonics at short distances is being engineered down.

And his core architectural insight is sound: if you are already moving to glass substrates for packaging reasons, and you are already moving to photonics for interconnect reasons, then embedding the photonic network directly in the glass substrate eliminates a layer of integration. Fewer interfaces means fewer failure points and lower cost. This is not a radical claim, it is almost obvious once you accept the two underlying trends.

The big bet and why it matters for Europe:

The risk here is real but so is the asymmetry. Silicon photonics has incumbency, ecosystem support, and a clear path to market through existing foundries. Ephos needs to build its own manufacturing capabilities from scratch while the design tools and supply chains mature around them. The curvature radius constraint means certain compact photonic components are off the table. And the timeline for chiplet-level photonic interconnects could stretch longer than anticipated as electrical approaches continue to improve.

But this is exactly the kind of bet that VC exists to make and that Europe specifically needs to be making. If Ephos is right about glass, they are not building a component supplier. They are potentially building the substrate on which the next generation of computing infrastructure runs. The same platform that connects AI accelerator chiplets could connect photonic quantum processors. The overlap Andrea described between classical and quantum requirements is a compounding advantage.

Europe has largely missed the semiconductor manufacturing wave and has no credible play in leading-edge logic. But advanced packaging and photonics are earlier in their trajectories. The fabs do not exist yet and standards are not locked in. A European company that masters glass-based photonic packaging could find itself at the centre of both the AI infrastructure buildout and the quantum computing transition. That is a rare positioning.

The question is not whether the technical risk is high. It is. The question is whether the potential reward justifies that risk, and whether this is the kind of strategic capability Europe should be cultivating regardless of the odds. Andrea’s confidence about wanting to build his own fab is either hubris or exactly the ambition required. Probably both.

Competition

We also didn’t cover competition, there are now several distinct material platforms competing to become the substrate of choice for integrated photonics, each with different strengths and trade-offs.

SMART Photonics in the Netherlands is the world’s first pure-play foundry for Indium Phosphide photonics semiconductors. The key advantage of InP is that it is the only material in the world that can create both active optical components such as lasers and amplifiers, as well as passive optical components like optical switches. This means you can integrate light sources directly on chip, which neither silicon nor glass can do natively. The company has received over €200M of Dutch and EU public technology funding and offers a mature ecosystem with process design kits and multi-project wafer runs. The limitation is that InP does not have the install base that silicon photonics has, and laser manufacturing has mainly been used for low volume markets like telecommunications.

LIGENTEC in Switzerland offers a 200mm silicon nitride foundry with ultra-low propagation losses of less than 0.5 dB/m and high-Q resonators above 20M. They have solved the volume manufacturing problem through a strategic partnership with X-FAB Silicon Foundries, resulting in Europe’s largest capacity foundry service for integrated photonic circuits. X-FAB can handle 100,000 new 200mm wafer starts per month, giving LIGENTEC access to serious scale. Silicon nitride strikes a balance: it cannot generate light like InP, but it offers transparency from visible to mid-IR wavelengths, reduced bending radius for compact designs, and access to non-linear and quantum applications. LIGENTEC is also developing cutting-edge technology to integrate thin-film lithium niobate on top of its silicon nitride platform for high-speed modulation.

Lightium is the first company to design and manufacture thin-film lithium niobate (TFLN) photonic chips at an industrial scale. The pitch is that silicon photonics have reached the physical limits of their material properties, while TFLN can scale for the foreseeable future, enabling data centres to increase their speeds 10x or more. TFLN offers exceptional electro-optical properties for modulation, but TFLN is a difficult material to process and has, up to now, been restricted to prototyping in academic and R&D settings. Lightium claims to have cracked the manufacturability problem and is transferring its TFLN process to a commercial CMOS fab.

How they compare to Ephos:

The core difference is manufacturing philosophy. SMART Photonics, LIGENTEC, and Lightium all use lithographic processes adapted from semiconductor manufacturing. This gives them access to existing fab infrastructure and established supply chains. Ephos uses femtosecond laser direct writing, which achieves massive scale through a different route. Parallelisation comes from two approaches: deploying multiple parallel beams per machine and operating multiple writing machines whose capital cost is a fraction of lithographic tools. The process is also single-step rather than the multi-step sequences required in lithography. These characteristics open up unique capabilities that traditional photonics foundries cannot easily replicate.

The advantage Ephos claims is extremely small interface losses of less than 2%, ideal for modular, scalable architectures connecting multiple chips. This fibre-to-chip coupling efficiency is critical for quantum applications where every photon matters. Glass also enables true 3D circuit architectures that lithographic approaches cannot easily achieve.

The trade-off is exactly what Andrea acknowledged in the interview: large curvature radii mean circuits become physically longer, and you cannot build compact ring resonators. LIGENTEC’s silicon nitride platform explicitly offers reduced bending radius, making very compact design possible. For applications where density matters more than interface losses, silicon nitride wins. But miniaturisation can backfire. The smaller your photonic chip, the less room you have for electronic component integration. Additionally, processes optimised for extreme density scale poorly from a cost perspective when applied to large areas, making them less competitive for chiplet integration in large panels.

Strategic positioning:

SMART Photonics owns the active component space. If you need on-chip lasers, you need InP. LIGENTEC owns the high-volume passive photonics space with their X-FAB partnership. Lightium is betting that TFLN’s modulation advantages will win for datacom applications as silicon runs out of headroom. Ephos is betting that glass’s interface losses and 3D capabilities will win for quantum photonics and potentially for the chiplet interconnect use case Andrea described. And then there is potentially gallium nitrite (GaN), where wavelength constraints loosen due short-reach datacom and hollow-core fibre, GaN could become a complete platform, offering native lasers, real electro-optic modulation, and transparency from UV to far infrared on a single material with an existing high-volume supply chain. That is a big if, but worth watching.

These are not necessarily competing bets. Think of it like a car: you do not choose between an engine, a gearbox, and wheels. You need all three, and each is optimised for a different function. A complete photonic system might use indium phosphide to generate light, because it is the only material that can produce lasers on chip. Silicon nitride to route that light around in dense, compact circuits, because it has tight bending radii and low loss. Thin-film lithium niobate to encode data onto the light at high speed, because it has the best electro-optic properties for modulation. And glass to connect everything to optical fibres with minimal loss, because it matches fibre properties almost perfectly. Each material owns a different function. They coexist rather than compete.

Glass can serve passive routing functions but is not limited to them. Ephos already builds active light manipulation on its glass platform, including what they claim is the most complex universal photonic processor demonstrated to date. With Fab-2, funded through the EU Chips Act, they are transitioning to fast electro-optic modulators integrated on glass.

The question for Ephos is timing. They are betting on glass for large-scale chiplet interconnects, which is a huge market but may take years to materialise. In the meantime, quantum photonics needs exactly what glass offers, ultra-low interface losses, right now. So should Ephos build their fab today for a quantum market that exists but is small, or wait for the chiplet market that is large but uncertain? That is the strategic tension.

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